1. Technical Field
The present invention relates in general to timing control within self-resetting circuitry and in particular to a system and method for providing selectable timing delay modes for self-resetting logic. More particularly, the present invention relates to adjusting the control path delay for self-resetting timing signals in response to process and structural variations and anomalies.
2. Description of the Related Art
Self-resetting logic circuitry was designed in part to eliminate the need to utilize a system clock signal with which to correctly synchronize all logic operations within very large scale integrated (VLSI) circuitry. Such self-resetting circuitry has generally been implemented utilizing Complementary Metal Oxide Semiconductor (CMOS) technology and is thus commonly referred to as SRCMOS. Further background information relating to self-resetting logic circuitry may be found with reference to U.S. Pat. No. 5,434,519, U.S. Pat. No. 5,565,798, and U.S. Pat. No. 5,329,176 which are incorporated herein by reference.
The timing signals generated by self-resetting logic techniques are characterized by having a fixed timing with respect to the input signals (often data input) which cause the triggering of self-reset circuits. Such fixed-timing signals are useful for internal clocking or strobing. When a self-reset initiated signal is utilized as a strobe (within a Programmable Logic Array (PLA) control module, for example) is it necessary to maintain the control path properly synchronized with related logic data transfer (the data path).
The self-timing characteristics of self-resetting logic suffers from the increased complexity of uncertain data signal arrival and pulse widths which may result from process variations or structural anomalies. These problems may be manageable under limited conditions where all signal interfaces are well-behaved, such as within a single macro or unit (an adder or SRAM, for example). However, when self-resetting logic is applied across a large and complex environment, such as within a microprocessor, the design environment is greatly complicated by noise, voltage differences, process variations, variability of inter-macro/unit wiring, etc. These complications may result in an unmanageable problem for synchronizing data and control paths within self-resetting interfaces across a chip design.
FIG. 1 depicts a conventional input detect circuit 100 for self-resetting (SR) CMOS circuitry. As is typical of SRCMOS circuitry, input detect circuit 100 is an edge detector for detecting dynamic logic input data. As seen in FIG. 1, input detect circuit 100 is constructed as a dynamic logic circuit having a pre-charge transistor 102 and an n-input NOR pull-down network 105, wherein n is the number of bits from bit (0) 106 through bit (n) 108. Pre-charge input detect node 110 is pre-charged to V.sub.dd 118 by pre-charge transistor 102, and conditionally discharged by foot transistor 107 upon receipt of one or more data bits from input data path 114.
When either a "True" or "Complement" of one or more of the input data 114 arrives, pre-charge input detect node 110 goes from high (pre-charged) to a logic low. A control path 124 is provided by an even number inversion module 125 which is comprised of inverters 120 and 122. Within control path 124 the arrival of data results in node 112 going high and reset node 104 going low and resetting the input NOR gate embodying pull-down network 105. This resetting of node 104 results in pre-charge transistor 102 being recharged such that input pre-charge input detect node is reset to a logic high after a fixed delay interval which demarcates the time span of control signal 116 as depicted in FIG. 1. The time delay through control path 124 is determined by the design of even number inversion module 125.
Since this self-resetting event is triggered by the arrival of incoming data 114, the generated signals at nodes 112 and 104 can be utilized to control or time other circuits that also accept incoming data 114. For example, the signal generated at node 112 may be utilized as a strobe signal in a PLA AND plane. The delay from the arrival of incoming data 114 to the generated strobe signal at node 112 is fixed. Therefore, any unexpected variation, such as a process variation, which causes the delay through control path 124 to depart from the designed delay may cause a collision between incoming data 114 and control signal 116. Due to the fixed nature of the timing utilized by self-resetting logic circuitry such as that illustrated in FIG. 1, it is difficult to correct the problem within the hardware itself.
From the foregoing it can be appreciated that a need exists for a system and method which provide multiple timing modes within self-resetting circuits to ensure that process variations and hardware anomalies do not result in disruption of proper timing and operation within such self-resetting circuits.